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Podcasts/Lex Fridman Podcast/Patterson, David

Patterson, David

Turing Award winner; professor of computer science at Berkeley; pioneer of RISC processor architecture and co-creator of RAID storage

David Patterson: Computer Architecture and Data Storage

Lex Fridman Podcast · Jun 27, 2020

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Core ideas

Patterson opens by explaining the five classic components of any computer (input/output, memory, and the processor's control and arithmetic units — likening the arithmetic unit to the body and control to the brain) and situates the microprocessor's invention roughly 50 years ago as the pivotal advance enabling room-sized computers to shrink into pocketable, radically cheaper, million-times-faster devices. He credits Moore's Law (Gordon Moore's 1965 observation, later revised to a doubling of transistor count every two years) as the engine behind this and describes the layered-abstraction philosophy underlying all of computer science — hiding complexity behind interfaces so each layer only needs to trust the contract of the one below it — noting the growing (and, in his view, healthy) trend toward open-sourcing not just software but hardware designs.

The heart of the conversation is Patterson's account of the RISC (Reduced Instruction Set Computer) revolution he co-led with John Hennessy at Stanford in the 1980s, for which they won the Turing Award. Against the prevailing wisdom that instruction sets should be complex and powerful (CISC) to ease programming, Patterson, Hennessy, and collaborators at IBM argued for radically simpler instruction sets on the bet that compilers — not programmers — would handle translation from high-level code, a bet enabled by UNIX proving operating systems themselves could be written in C rather than hand-tuned assembly. The core technical argument, once formalized, was that execution time decomposes into (instructions executed) × (average clock cycles per instruction) × (clock cycle time): RISC required executing roughly 25–50% more instructions, but each ran in far fewer clock cycles (since CISC machines needed slow hardware interpreters to decode complex instructions), yielding a net 3–4x speedup. The idea was fiercely, "violently" debated at conferences in the 1980s, and Intel ultimately preserved its proprietary, software-compatible x86 CISC instruction set commercially by having chips translate CISC instructions into RISC-like micro-operations in hardware on the fly — while ARM (originally directly influenced by Berkeley's RISC papers) became the dominant clean RISC architecture, prized for energy efficiency since it avoids that translation overhead, making it the natural fit for battery-powered phones and power-constrained cloud datacenters. Patterson highlights RISC-V, developed at Berkeley around 2010 (led by Krste Asanović, Andrew Waterman, and Yunsup Lee) as the next step: an open, freely licensed instruction set specification (unlike proprietary x86 or ARM) built around a minimal ~40-instruction core with optional extensions, enabling open-source hardware implementations the way Linux enabled open-source software — a design he considers genuinely elegant ("small is beautiful") precisely because it resists the tendency of proprietary instruction sets to accumulate bloat over decades. He predicts RISC-V could become dominant particularly in Internet of Things/embedded applications where no incumbent controls the software stack, and notes its adoption grew from ~50 people at its first 2015 conference to ~1,700 by the most recent one.

On the present moment in computer architecture, Patterson argues Moore's Law is genuinely slowing (transistor counts are no longer doubling on schedule, evidenced by comparing actual transistor counts across recent years), which is forcing a shift away from general-purpose performance gains toward domain-specific accelerators — and, fortuitously, this coincides with the machine learning revolution, whose core computational primitive (matrix multiplication) is exactly the kind of workload accelerators excel at and which turns out to be broadly applicable across nearly every domain rather than narrowly niche. He frames this as a second "golden age" of computer architecture comparable to the RISC era, occurring simultaneously at the hardware layer (domain-specific chips) and the software layer (frameworks like TensorFlow and PyTorch raising the abstraction level), and stresses that hardware-only efforts which neglect the software stack fail commercially — illustrating this with Intel's cancellation of its Nervana chip line in favor of acquiring Habana Labs (whose hardware-plus-software combination scored well on MLPerf, a benchmark suite Patterson helped create). He draws a direct parallel between MLPerf and the earlier SPEC benchmark effort that resolved competing, unverifiable performance claims among rival RISC vendors in the 1980s, arguing that fields lacking agreed benchmarks (he cites computer vision before David Martin's early benchmarking work, which predated ImageNet) struggle to make verifiable progress, and that social media era transparency now makes misleading marketing claims far riskier than in the past. On quantum computing, Patterson is skeptical of near-term hype, citing two national reports estimating error-corrected quantum computing is roughly a decade away (circa 2030) and useful only for a narrow set of applications, not general-purpose computation — and he pushes back on the claim (attributed to Jim Keller) that he denies semiconductor progress continues, clarifying that his actual claim is narrowly quantitative: transistor counts are no longer doubling every two years as Moore's original prediction specified, regardless of how the term gets reinterpreted for marketing purposes.

Patterson also recounts co-developing RAID (Redundant Array of Inexpensive Disks) with Randy Katz and Garth Gibson in 1988: motivated by the arrival of cheap, small hard drives for early Macintoshes, they proposed replacing single large "washing machine"-sized mainframe disks with many small inexpensive ones for better speed and cost — until an IBM reviewer pointed out the combined failure rate would be catastrophic (roughly every two weeks instead of yearly), prompting them to add redundancy so some drives could fail without data loss, which also improved overall reliability. He notes storage reliability concerns are far more consequential than computational error, since a computational mistake just requires rerunning a program while lost data is often irreplaceable, and that RAID-style redundancy concepts persist even as the underlying media has shifted from spinning magnetic disks to flash/semiconductor storage in most devices (with magnetic disks still more cost-effective at cloud scale). Reflecting on career and teaching, Patterson notes that of five Berkeley colleagues who won the campus's Distinguished Teaching Award, three (himself, Manuel Blum, and Richard Karp) also won the Turing Award, arguing (echoing Feynman's critique of teaching-free research institutes) that being forced to explain fundamentals to inquisitive students sharpens research thinking rather than detracting from it. He credits competitive wrestling (at El Camino College and UCLA) with building both a personal confidence that carries into intellectual argument (willingness to stand up in RISC-style debates) and team-building skills from coaches who treated an individual sport as a collective enterprise. Asked what a life well-lived looks like, he cites a colleague's line that success is measured not by "the number of zeros in your bank account" but "the number of inches in the obituary," and says his own proudest legacies are relationships — his marriage of 50+ years, family, students, and mentorship — rather than his hundreds of published papers.

Excerpts

On the core RISC vs. CISC performance argument:

“The way you measure performance is how long does it take a program to run... you could factor that into three factors: how many instructions did it take to execute, how many clock cycles per instruction on average, and how long is a clock cycle. In these RISC-CISC debates... we'd have to execute maybe 25 or 50 percent more instructions, but the clock cycles per instruction is much less — that's where the win would come.”

On RISC-V's minimalist design philosophy:

“They hit upon this idea of having a subset of instructions — a nice, simple instruction subset, like 40-ish instructions that all software can run just on those forty instructions — and then they provide optional features... What's happened in the past for the proprietary instruction sets is when they add new instructions it becomes a required piece, so all microprocessors in the future have to use those instructions. It's kind of like, as people get older they gain weight.”

On what he's actually proud of at the end of a research career:

“A friend, Randy Katz, said this: when it's time to sign off, the measure isn't the number of zeros in your bank account, it's the number of inches in the obituary in the New York Times... I came into this job assuming it wasn't going to be the papers, it was going to be relationships with the people over time that I would value — and that was a correct assessment.”